Parity bits are commonly used to verify that a memory is working properly. By adding the extra bit or bits to a data word, the data can be verified (and, in certain instances corrected) by using the formula that initially generated the bits.
Generally speaking, parity is useful for checking data. However, if one also wishes to check for errors in the addressing circuitry, more is needed. For example, if the processor issues a command to address a particular location in memory and, as a result of a hardware error, a different location is addressed, a parity check will not reveal the error if the data is otherwise correct. Address errors may arise from defects in such components as the address bus and the address decoders.
One solution to this problem is to write unique data patterns into each location in the memory, such that no two locations contain the same pattern. Upon reading the data, if an erroneous pattern is detected, it can be concluded that the error exists either in the data or the address or both. A typical data pattern is the actual address of the accessed location, i.e., the data 00101 would be written in memory location 00101. To verify both polarities of data errors, such as stuck-at-0 and stuck-at-1, the one's complement of the address can be written to memory in a second pass.
The approach outlined above is satisfactory where the bit-length of the data word (or other data unit) is equal to or greater than that of the address. If they are equal, the data simply becomes the value of the address. In the event the data word is larger, additional dummy bits can be added to the address to compose a suitable data word.
However, where the bit-length of the address is greater than that of the data, the data word can no longer be unique with respect to each address. This latter situation is common in many of the popular microprocessors in use today, e.g., the 80X86 and the 680X0 families of microprocessors, where the bit-length of the address can be as much as twice that of the data. For example, as shown in FIG. 1, if the data has a bit-length of 3 (yielding 8 possible combinations) and the address has a bit-length of 5 (resulting in 32 possible addressable locations), the three-bit data patterns will repeat four times, resulting in four otherwise identical segments. If there is an error in the addressing circuitry, causing the memory to read from a different segment, the data may nevertheless appear correct as it would otherwise be the same. Thus, in order to detect an addressing error, it is necessary to distinguish between the data in the four segments.
Therefore, it would be desirable to provide a method of generating data that can assist in detecting errors in both the data and the address in memories where the address bit-length is greater than the data word bit-length.